optoelectronic world
OP TICAL
behave in vivo similarly to convention- signed and engineered with safe, easy INTERCONNECTS al tattoo inks, histological and clinical tattoo removal in mind,” Anderson evaluation following tattoo applica- said. Further development of the pro- Light pipes seen as tion and removal showed no adverse totype inks is being handled by Free- skin reactions, no allergic reactions, dom- 2 (Philadelphia, PA), a startup es- path to gigascale no infections, no inflammation, and tablished specifically to commercialize no adverse systemic reactions. this technology. integration
“These are the first tattoo inks de- Kathy Kincade An estimated 800 scientists, engineers,
and other professionals will meet next
month for the ninth annual IEEE Inter-
national Interconnect Technology Con-
ference (IITC; June 5– 7, San Francisco,
CA), focused on enabling the intercon-
nects in semiconductor circuitry keep
up with the pace of Moore’s Law. One
of the more visionary ideas they will en-
counter involves replacing current elec-
trical interconnects between chips and
circuit boards with similarly sized “light
pipes” that will carry both electronic
and optical signals.
Semiconductor chips with 90 nm fea-
ture sizes are currently in volume pro-
duction with 65 nm chips already in early
production. Feature sizes of 45 nm tech-
nology are expected to be in production
in two or three years with 32 nm project-
ed for the beginning of the next decade.
While transistor speed has tradition-
ally been considered the limiting fac-
tor for chip performance, the speed
at which information can travel along
interconnects looms as the new major
limiting factor. The electrical resis-
tance of metal lines increases as they are
made thinner, and capacitive coupling
arises among adjacent lines when they
are spaced closely together, further in-
hibiting the passage of signals.
“I think it’s fair to say the interconnect
issue is one of the most difficult chal-
lenges in the entire field of engineering,”
said Stephen Luce, IITC 2006 publicity
chairman and IBM distinguished engi-
neer and chief technical executive for the
company’s Essex Junction, VT, wafer fab.
Nevertheless, one does not have to
look far along the exponential growth
curve to the point where billions, rath-
er than millions of transistors will be
packed onto a chip, with concomitant
stresses on speed and bandwidth. The
International Technology Roadmap for
Semiconductors projects that chipboard
speed will approach 56 GHz when fea-
ture sizes shrink to 18 nm, which implies
that new interconnect technologies will
be required, according to Oluwafemi
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